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A45L9332A Series
Preliminary
Document Title 256K X 32Bit X 2 Banks Synchronous Graphic RAM Revision History
Rev. No.
0.0 0.1
256K X 32 Bit X 2 Banks Synchronous Graphic RAM
History
Initial issue Update AC and DC data specification
Issue Date
August 21, 2001 October 22, 2001
Remark
Preliminary
PRELIMINARY
(October, 2001, Version 0.1)
AMIC Technology, Inc.
A45L9332A Series
Preliminary
Features
n n n n JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Dual banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2,3) - Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM 0-3 for byte masking Auto & self refresh 32ms refresh period (2K cycle) n 100 Pin QFP, LQFP (14 X 20 mm)
256K X 32 Bit X 2 Banks Synchronous Graphic RAM
Graphics Features
n SMRS cycle - Load mask register - Load color register n Write Per Bit (Old Mask) n Block Write (8 Columns)
n n n n n
General Description
The A45L9332A is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 X 262,144 words by 32 bits, fabricated with AMIC's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. Write per bit and 8 columns block write improves performance in graphics system.
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A45L9332A Series
Pin Configuration
VSSQ
DQ31
DQ30
VSSQ 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
DQ 3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ 21 VSSQ DQ 22 DQ 23 VDDQ DQM0 DQM2 WE CAS RAS CS BA(A10) A8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
81 80 79 78 77 76 75 74 73 72 71 70 69
DQ29
VDD
VSS
DQ2
DQ1
DQ0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ28 VDDQ DQ 27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC DQM3 DQM1 CLK CKE DSF NC A9
A45L9332AE A45L9332AF
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A0
A1
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A2
A4
A5
A6
VDD
A3
A7
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A45L9332A Series
Block Diagram
DQMi BLOCK WRITE CONTROL LOGIC CLK
MASK REGISTER WRITE CONTROL LOGIC MASK CLOCK REGISTER
MUX
INPUT BUFFER
CKE
COLUMN MASK DQMi TIMMING REGISTER
DQi (i=0~31)
CS RAS
SENSE AMPLIFIER
LATENCY & BURST LENGTH
PROGRAMING REGISTER
CAS
256K x 32 CELL ARRAY
256K x 32 CELL ARRAY
WE
DSF ROW DECORDER BANK SELECTION
DQMi
SERIAL COUNTER
COLUMN ADDRESS BUFFER
ROW ADDRESS BUFFER
REFRESH COUNTER
ADDRESS REGISTER
CLOCK
ADDRESS (A0~A10)
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INPUT BUFFER
COLUMN DECORDER
A45L9332A Series
Pin Descriptions
Symbol CLK CS Name System Clock Chip Select Description Active on the positive going edge to sample all inputs. Disables or Enables device operation by masking or enabling all inputs except CLK, CKE and DQMi Masks system clock to freeze operation from the next clock cycle. CKE Clock Enable CKE should be enabled at least one clock + t ss prior to new command. Disable input buffers for power down in standby. Row / Column addresses are multiplexed on the same pins. A0~A9 Address Row address : RA0~RA9, Column address: CA0~CA7 Selects bank to be activated during row address latch time. A10(BA) Bank Select Address Selects band for read/write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE DQMi DQi DSF VDD/VSS VDDQ/VS SQ NC Write Enable Enables write operation and Row precharge. Makes data output Hi-Z, t SHZ after the clock and masks the output. Data Input/Output Mask Blocks data input when DQM active. (Byte Masking) Data Input/Output Define Special Function Power Supply/Ground Data Output Power/Ground No Connection Data inputs/outputs are multiplexed on the same pins. Enables write per bit, block write and special mode register set. Power Supply: +3.3V0.3V/Ground Provide isolated Power/Ground to DQs for improved noise immunity.
CAS
Column Address Strobe
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A45L9332A Series
Absolute Maximum Ratings*
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V Voltage on VDD supply relative to VSS (VDD, VDDQ ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V Storage Temperature (TSTG) . . . . . . . . . -55C to +150C Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C X 10sec Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Capacitance (TA=25C, f=1MHz)
Parameter Input Capacitance Symbol CI1 CI2 Data Input/Output Capacitance CI/O A0 to A9, BA CLK, CKE, DQMi, DSF Condition Min 2 2 2 Typ Max 4 4 6 Unit pF pF pF
CS , RAS , CAS , WE ,
DQ0 to DQ15
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V) Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Output Loading Condition Symbol VDD,VDDQ VIH VIL VOH VOL IIL IOL Min 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 3.0 0 See Figure 1 Max 3.6 VDD+0.3 0.8 0.4 5 5 Unit V V V V V A A Note 1 IOH = -2mA IOL = 2mA Note 2 Note 3 Note
Note: 1. VIL (min) = -1.5V AC (pulse width 5ns). 2. Any input 0V VIN VDD + 0.3V, all other pins are not under test = 0V 3. Dout is disabled, 0V Vout VDD
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board. Parameter Decoupling Capacitance between VDD and VSS Decoupling Capacitance between VDDQ and VSSQ Symbol CDC1 CDC2 Value 0.1 + 0.01 0.1 + 0.01 Unit F F
Note: 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip.
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A45L9332A Series
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Symbol Parameter Operating Current Icc1 Icc2 P Icc2 PS ICC2N (One Bank Active) Precharge Standby Current in powerdown mode Test Conditions Burst Length = 1 tRC tRC(min), tCC tCC(min), IOL = 0mA CKE VIL(max), tCC = 15ns CKE VIL(max), CKL VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Precharge Standby Current in non power-down mode Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable. ICC3 P ICC3 PS ICC3N Active Standby Current in powerdown mode Active Standby current in non power-down mode (One Bank Active) CKE VIL(max), tCC = 15ns CKE VIL(max), CKE VIL(max) tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable. Operating Current (Burst Mode) IOL = 0mA, Page Burst All bank Activated, tCCD = tCCD (min) 3 2 3 ICC5 ICC6 ICC7 Refresh Current Self Refresh Current Operating Current (One Bank Block Write) tRC tRC (min) CKE 0.2V tCC tCC (min), IOL=0mA, tBWC(min) 240 2 310 150 280 230 120 180 4 220 190 250 mA 210 120 120 mA mA mA 2 1 40 15 6 6 60 mA CAS Latency 3 2 -6 230 Speed -7 210 260 4 4 35 mA -8 170 160 mA mA 1 Unit Notes
ICC2NS
mA
ICC3NS
ICC4
Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min). 2. Refresh period is 32ms. Addresses are changed only one time during tCC(min).
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A45L9332A Series
AC Operating Test Conditions
(VDD = 3.3V 0.3V, TA = 0C to +70C) Parameter AC input levels Input timing measurement reference level Input rise and all time (See note3) Output timing measurement reference level Output load condition Value VIH/VIL = 2.4V/0.4V 1.4V tr/tf = 1ns/1ns 1.4V See Fig.2
3.3V 1200 Output OUTPUT 870 3pF VOH(DC) = 2.4V, IOH = -2mA VOL(DC) = 0.4V, IOL = 2mA VTT =1.4V 50 ZO=50 30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
AC Characteristics
(AC operating conditions unless otherwise noted) -6 Symbol Parameter CAS Latency 3 tCC CLK cycle time 2 CLK to valid tSAC Output delay tOH Output data hold time 3 tCH CLK high pulse width 2 2 2.5 2.5 3 2.5 2.5 3 7.5 2.5 3 ns 3 7 ns 2 3 5.5 Min 6 1000 8 6 Max Min 7 1000 10 6.5 ns 1,2 -7 Max Min 8 1000 ns 1 -8 Unit Max Note
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A45L9332A Series
AC Characteristics (continued)
(AC operating conditions unless otherwise noted) -6 Symbol Parameter CAS Latency 3 tCL CLK low pulse width 2 3 tSS Input setup time 2 3 tSH Input hold time 2 3 tSLZ CLK to output in Low-Z 2 CLK to output tSHZ In Hi-Z 2 7.5 7 3 5.5 6 6.5 ns 1 1 1 ns 2 1 1 1 ns 3 2 2.5 Min 2.5 3 2 2.5 ns 3 Max Min 2.5 3 ns 3 -7 Max Min -8 Unit Max Note
*All AC parameters are measured from half to half. Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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A45L9332A Series
Operating AC Parameter
(AC operating conditions unless otherwise noted) Symbol Parameter CAS Latency 3 tRRD(min) Row active to row active delay 2 3 tRCD(min) RAS to CAS delay Row precharge time 2 3 tRP(min) 2 3 tRAS(min) Row active time tRAS(max) 2 3 2 3 tRC(min) Row cycle time 2 3 tCDL(min) Last data in new col. Address delay 2 3 tRDL(min) Last data in row precharge 2 3 tBDL(min) Last data in to burst stop 2 3 tCCD(min) Col. Address to col. Address delay 2 3 tBPL(min) Block write data-in to PRE command 2 3 tBWC(min) Block write cycle time 2 3 Number of valid output data 2 1 2 1 CLK CLK CLK 1,3 4 2 CLK 1 CLK 3 1 CLK 2 2 1 2 2 2 2 CLK 2 CLK 2 11 100 10 7 9 7 CLK 1 2 3 3 8 2 3 2 3 3 7 5 2 2 2 2 2 6 5 CLK 1 CLK 1 CLK 1 CLK 1 Version -6 -7 -8 Unit Note
s
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. This parameter means minimum CAS to CAS delay at block write cycle only. 4. In case of row precharge interrupt, auto precharge and read burst stop.
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Simplified Truth Table
Command Register Refresh Mode Register Set Special Mode Register Set Auto Refresh Self Refresh Bank Active & Row Addr. Entry Exit H L H X H L H L L H L L L L L L L H X L H L H L H L H X L H H H H L H X X H X V X X X H X H X H X X L H X H L L L H H H X X H X V X H H X H H L L L L H X X H X V X X L H H H H H Bank Selection Both Banks Clock Suspend or Active Power Down Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command L H H H H H L H X L H L L X X X V X X X X X X X X V X X X 8 X X X X X H L L H L X X X X X V X V V V V Row Addr. L H L H L H X L H X Column Addr. X X L X X L L L L CKEn-1 CKEn
CS
RAS CAS
WE DSF DQM A10 A9 A8~A0 Notes
L H X OP CODE 1,2 1,2,7 3 3 3 3 4,5 4,5,9 4 4,6
Write Per Bite Disable Write Per Bit Enable
Read & Auto Precharge Disable Column Addr. Auto Precharge Enable Write & Auto Precharge Disable Column Addr. Auto Precharge Enable Block Write & Auto Precharge Disable Column Addr. Auto Precharge Enable Burst Stop Precharge
Column 4,5 Addr. 4,5,6,9 Column 4,5 Addr. 4,5,6,9 7
(V = Valid, X = Don't Care, H = Logic High, L = Logic Low) Note : 1. OP Code : Operand Code A0~A10 : Program keys. (@MRS) Color register exists only one per DQi which both banks share. So dose Mask Register. Color or mask is loaded into chip through DQ pin. 2. MRS can be issued only at both banks precharge state. SMRS can be issued only if DQ's are idle. A new command can be issued at the next clock of MRS/SMRS. 3. Auto refresh functions as same as CBR refresh of DRAM. The automatical precharge without Row precharge command is meant by "Auto". Auto/Self refresh can be issued only at both precharge state.
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A45L9332A Series
Simplified Truth Table
4. A10 : Bank select address. If "Low" at read, (block) write, Row active and precharge, bank A is selected. If "High" at read, (block) write, Row active and precharge, bank B is selected. If A9 is "High" at Row precharge, A10 is ignored and both banks are selected. 5. It is determined at Row active cycle. whether Normal/Block write operates in write per bit mode or not. For A bank write, at A bank Row active, for B bank write, at B bank Row active. Terminology : Write per bit = I/O mask (Block) Write with write per bit mode = Masked (Block ) Write 6. During burst read or write with auto precharge, new read/ (block) write command cannot be issued. Another bank read/(block) write command can be issued at tPR after the end of burst. 7. Burst stop command is valid only t full page burst length. 8. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2) 9. Graphic features added to SDRAM's original features. If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32 DQ's.
SGRAM vs SDRAM
Function DSF L MRS H L Bank Active SGRAM Function MRS SMRS with Write per bit Disable IF DSF is low, SGRAM functionality is identical to SDRAM functionality. SGRAM can be used as an unified memory by the appropriate DSF control SDRAM = Graphic Memory + main Memory Bank Active H Bank Active with Write per bit Enable Normal Write Block Write L Write H
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A45L9332A Series
Mode Register Filed Table to Program Modes
Register Programmed with MRS Address Function A10 RFU A9 W.B.L
(Note 2)
A8 TM
A7
A6
A5 CAS Latency
A4
A3 BT
A2
A1 Burst Length
A0
(Note 1)
Test Mode A8 0 0 1 1 A7 0 1 0 1 Type Mode Register Set Vendor Use Only A6 0 0 0 0 1 1 1 1
CAS Latency A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved 2 3 Reserved Reserved Reserved Reserved
Burst Type A3 0 1 Type Sequential Interleave A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
Burst Length A0 0 1 0 1 0 1 0 1 BT=0 1 2 4 8 Reserved Reserved Reserved 256(Full) BT=1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved (Note 3)
Write Burst Length A9 0 1 Length Burst Single Bit
Special Mode Register Programmed with SMRS Address Function A10 A9 X A8 A7 A6 LC A5 LM A4 A3 A2 X A1 A0
Load Color A6 0 1
Load Mask Function Disable Enable (Note 4)
Function A5 Disable Enable 0 1
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = "H", DQM = "H" and the other pins are NOP condition at inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200s. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 may be changed. The device is now ready for normal operation. Note : 1. RFU(Reserved for Future Use) should stay "0" during MRS cycle. 2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 3. The full column burst (256bit) is available only at Sequential mode of burst type. 4. If LC and LM both high (1), data of mask and color register will be unknown.
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Burst Sequence (Burst Length = 4)
Initial address Sequential A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 0 3 2 2 3 0 1 3 2 1 0 Interleave
Burst Sequence (Burst Length = 8)
Initial address Sequential A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 Interleave
Pixel to DQ Mapping (at BLOCK WRITE)
Column address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 3 Byte I/O31 - I/O24 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 2 Byte I/O23 - I/O16 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 1 Byte I/O15 - I/O8 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 0 Byte I/O7 - I/O0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
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Device Operations
Clock (CLK) The clock input is used as the reference for all SGRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of set up and hold time around positive edge of the clock for proper functionality and ICC specifications. Clock Enable (CLK) The clock enable (CKE) gates the clock onto SGRAM. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended form the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When both banks are in the idle state and CKE goes low synchronously with clock, the SGRAM enters the power down mode form the next clock cycle. The SGRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "tSS + 1 CLOCK" before the high going edge of the clock, then the SGRAM becomes active from the same clock edge accepting all the input commands. Bank Select (A10) This SGRAM is organized as two independent banks of 262,144 words X 32 bits memory arrays. The A10 inputs is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. When A10 is asserted low, bank A is selected. When A10 is asserted high, bank B is selected. The bank select A10 is latched at bank activate, read, write mode register set and precharge operations. Address Input (A0 ~ A9) The 18 address bits required to decode the 262,144 word locations are multiplexed into 10 address input pins (A0~A9). The 10 bit row address is latched along with RAS and A10 during bank activate command. The 8 bit column address is latched along with CAS , WE and A10 during read or write command. NOP and Device Deselect When RAS , CAS and WE are high, the SGRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock like bank activate, burst Mode Register Set (MRS) The mode register stores the data for controlling the various operation modes of SGRAM. It programs the CAS latency, addressing mode, burst length, test mode and various vendor specific options to make SGRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SGRAM. The mode register is written by asserting low on CS , RAS , read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS , CAS and WE , DSF and all the address inputs are ignored. Power-Up The following sequence is recommended for POWER UP 1. Power must be applied to either CKE and DQM inputs to pull them high and other pins are NOP condition at the inputs before or along with VDD (and VDDQ) supply. The clock signal must also be asserted at the same time. 2. After VDD reaches the desired voltage, a minimum pause of 200 microseconds is required with inputs in NOP condition. 3. Both banks must be precharged now. 4. Perform a minimum of 2 Auto refresh cycles to stabilize the internal circuitry. 5. Perform a MODE REGISTER SET cycle to program the CAS latency, burst length and burst type as the default value of mode register is undefined. At the end of one clock cycle from the mode register set cycle, the device is ready for operation. When the above sequence is used for Power-up, all the out-puts will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence. Cf.) Sequence of 4 & 5 may be charged.
CAS , WE and DSF (The SGRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0~A9 and A10 in the same cycle as CS , RAS , CAS , WE and DSF going low is the data written in the mode register. One clock cycle is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length field uses A0~A2, burst type uses A3, addressing mode uses A4~A6, A7~A8 and A10 are used for vendor specific options or test mode. And the write burst length is programmed using A9. A7~A8 and A10 must be set to low for normal SGRAM operation. Refer to table for specific codes for various burst length, addressing modes and CAS latencies.
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Device Operations (continued)
Bank Activate The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of bank activation. tRCD(min) is an internal timing parameter of SGRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. The SGRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. Also the noise generated during sensing of each bank of SGRAM is high requiring some time for power supplies recover before the other bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating different banks. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by tRAS(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS(max). The number of cycles for both tRAS(min) and tRAS(max) can be calculated similar to tRCD specification. Burst Read The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued. The first output appears CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid only at full page burst length where the output dose not go into high impedance at the end of burst and the burst is wrap around. Burst Write The burst write command is similar to burst read command, and is used to write data into the SGRAM consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS , CAS and
WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. The writing can not complete to burst length. The burst write can be terminated by issuing a burst read and DQM for blocking data inputs or burst write in the same or the other active bank. The burst stop command is valid only at full page burst length where the writing continues at the end of burst and the burst is wrap around. The write burst can also be terminated by using DQM for blocking data and precharging the bank "tRDL" after the last data input to be written into the active row. See DQM OPERATION also.
DQM Operation The DQM is used to mask input and output operation. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in the read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock, therefore the masking occurs for a complete cycle. The DQM signal is important during burst interrupts of write with read or precharge in the SGRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. DQM is also used for device selection, byte selection and bus control in a memory system. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31. DQM masks the DQ's by a byte regardless that the corresponding DQ's are in a state of WPB masking or Pixel masking. Please refer to DQM timing diagram also. Precharge The precharge operation is performed on an active bank by asserting low on CS , RAS , WE and A9 with valid A10 of the bank to be precharged. The precharge command can be asserted anytime after tRAS(min) is satisfied from the bank activate command in the desired bank. "tRP" is defined as the minimum time required to precharge a bank. The minimum number of clock cycles required to complete row precharge is calculated by dividing "tRP" with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge
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Device Operations (continued)
command is asserted. The maximum time any bank can be active is specified by tRAS(max). Therefore, each bank has to be precharged within tRAS(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc, is possible only when both banks are in idle state. Auto Precharge The precharge operation can also be performed by using auto precharge. The SGRAM internally generates the timing to satisfy tRAS(min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A9. If burst read or burst write command is issued with low on A9, the bank is left active until a new command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state. Both Banks Precharge Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS , RAS and data retention and low power operation of SGRAM. In self refresh mode, the SGRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption. The self refresh mode is entered from all banks idle state by asserting low on CS , RAS , CAS and CKE with high on WE . Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the self refresh. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of "tRC" before the SGRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to used burst 2048 auto refresh cycles immediately after exiting self refresh. Define Special Function (DSF) The DSF controls the graphic applications of SGRAM. If DSF is tied to low, SGRAM function is 256K X 32 X 2 Bank SDRAM. SDRAM can be used as an unified memory by the appropriate DSF command. All the graphic function mode can be entered only by setting DSF high when issuing commands which otherwise would be normal SDRAM commands. SDRAM functions such as RAS Active, Write, and WCBR change to SGRAM functions such as RAS Active with WPB, Block Write and SWCBR respectively. See the sessions below for the graphic functions that DSF controls. Special Mode Register Set (SMRS) There are two kinds of special mode registers in SGRAM. One is color register and the other is mask register. Those usage will be explained at "WRITE PER BIT" and "BLOCK WRITE" session. When A5 and DSF goes high in the same cycle as CS , RAS , CAS and WE going low, load mask register (LMR) process is executed and the mask registers are filled with the masks for associated DQ's through DQ pins. And when A6 and DSF goes high in the same cycle as CS , RAS , CAS and WE going low, load color register (LCR) process is executed and the color register is filled with color data for associated DQ's through the DQ pins. If both A5 and A6 are high at SMRS, data of mask and color cycle is required to complete the write in the mask register and the color register at LMR and LCR respectively. The next clock of LMR or LCR, a new commands can be issued. SMRS, compared with MRS, can be issued at the active state under the condition that DQ's are idle. As in write operation, SMRS accepts the data needed through DQ pins. Therefore it should be attended not to induce bus contention. The more detailed materials can obtained by referring corresponding timing diagram.
WE with high on A9 after both banks have satisfied tRAS(min) requirement, performs precharge on both banks. At the end of tRP after performing precharge all, both banks are in idle state.
Auto Refresh The storage cells of SGRAM need to be refreshed every 32ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS , RAS and CAS with high on CKE and WE . The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by "tRC(min)". The minimum number of clock cycles required can be calculated by driving "tRC" with clock cycle time and then rounding up to the next higher integer. The auto refresh command must be followed by NOP's until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SGRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or a burst of 2048 auto refresh cycles once in 32ms. Self Refresh The self refresh is another refresh mode available in the SGRAM. The self refresh is the preferred refresh mode for
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Device Operations (continued)
Write Per Bit Write per bit (i.e. I/O mask mode) for SGRAM is a function that selectively masks bits of data being written to the devices. The mask is stored in an internal register and applied to each bit of data written when enabled. Bank active command with DSF = High enabled write per bit operations is stored in the mask register accessed by SWCBR (Special Mode Register Set Command). When a mask bit = 1, the associated data bit is written when a write command is executed and write per bit has been enabled for the bank being written. When a mask bit = 0, the associated data bit is unaltered when a write command is executed and the write per bit has been enabled for the bank being written. No additional timing conditions are required for write per bit operations. Write per bit writes can be either single write, burst writes or block writes. DQM masking is the same for write per bit and non-WPB write. Block Write Block write is a feature allowing the simultaneous writing of consecutive 8 columns of data within a RAM device during a single access cycle. During block write the data to be written comes from an internal "color" register and DQ I/O pins are used for independent column selection. The block of column to be written is aligned on 8 column boundaries and is defined by the column address with the 3 LSB's ignored. Write command with DSF = 1enables block write for the associated bank. A write command with DSF = 0 enables normal write for the associated bank. The block width is 8 column where column = "n" bits for by "n" part. The color register is the same width as the data port of the chip. It is written via a SWCBR where data present on the DQ pin is to be coupled into the internal color register. The color register provides the data masked by the DQ column select, WPB mask (If enabled), and DQM byte mask. Column data masking (Pixel masking) is provided on an individual column basis for each byte of data. The column mask is driven on the DQ pins during a block write command. The DQ column mask function is segmented on a per bit basis (i.e. DQ[0:7] provides the column mask for data bits[0:7], DQ[8:15] provides the column mask for data bits[8:15], DQ0 masks column[0] for data bits[0:7], DQ9 masks column [1] for data its [8:15], etc). Block writes are always non-burst, independent of the burst length that has been programmed into the mode register. Back to back block writes are allowed provided that the specified block write cycle time (tBWC) is satisfied. If write per bit was enabled by the bank active command with DSF = 1, then write per bit masking of the color register data is enabled. If write per bit was disabled by a bank active command with DSF = 0, the write per bit masking of the color register data is disabled. DQM masking provides independent data byte masking during block write exactly the same as it does during normal write operations, except that the control is extended to the consecutive 8 columns of the block write. Timing Diagram to Illustrate tBWC
0 Clock CKE CS
1
2
High
RAS
CAS
WE
DSF 1 CLK BW
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Summary of 2M Byte SGRAM Basic Features and Benefits
Features 256K X 32 X 2 SGRAM Benefits Better interaction between memory and system without wait-state of asynchronous DRAM. Interface Synchronous High speed vertical and horizontal drawing. High operation frequency allows performance gain for SCROLL, FILL, and BitBLT. Bank Page Depth / 1 Row Total Page Depth Burst Length (Read) 2 ea 256 bit 2048 bytes 1,2,4,8 Full Page 1,2,4,8 Full Page BRSW Burst Type CAS Latency Block Write Color Register Mask Register Sequential & Interleave 2,3 8 Columns 1 ea. 1 ea. DQM0-3 Mask function Write per bit Pseudo-infinite row length by on-chip interleaving operation. Hidden row activation and precharge. High speed vertical and horizontal drawing. High speed vertical and horizontal drawing Programmable burst of 1,2,4,8 and full page transfer per column addresses. Programmable burst of 1,2,4,8 and full page transfer per column addresses. Switch to burst length of 1 at write without MRS Compatible with Intel and Motorola CPU based system. Programmable CAS latency. High speed FILL, CLEAR, Text with color registers. Maximum 32 byte data transfers (e.g. for 8bpp : 32 pixels) with plane and byte masking functions. A and B bank share. Write-per-bit capability (bit plane masking). A and B banks share. Byte masking (pixel masking for 8bpp system) for data-out/in Each bit of the mask register directly controls a corresponding bit plane.
Burst Length (Write)
Pixel Mask at Block Write Byte masking (pixel masking for 8bpp system) for color by DQi
Basic feature And Function Descriptions 1. CLOCK Suspend
1) Click Suspended During Write (BL=4)
2) Clock Suspended During Read (BL=4)
CLK CMD CKE Masked by CKE Internal CLK Masked by CKE WR RD
DQ(CL2) DQ(CL3)
D0 D0
D1 D1
D2 D2 Not Written
D3 D3
Q0
Q1 Q0
Q2 Q1
Q3 Q2 Suspended Dout Q3
Note: CLK to CLK disable/enable=1 clock
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2. DQM Operation
1) Write Mask (BL=4)
2) Read Mask (BL=4)
CLK CMD WR RD
DQMi Masked by CKE DQ(CL2) DQ(CL3) D0 D0 D1 D1 D3 D3 Q0 Hi-Z Hi-Z Masked by CKE Q1 Q1 Q3 Q2 Q3
DQM to Data-in Mask = 0CLK
DQM to Data-out Mask = 2
2) Read Mask (BL=4)
CLK CMD CKE RD
DQM DQ(CL2) DQ(CL3) Q0 Hi-Z Hi-Z Q2 Q1 Hi-Z Hi-Z Q4 Q3 Hi-Z Hi-Z Q6 Q5 Q7 Q6 Q8 Q7
* Note : 1. There are 4 DQMi (I=0~3).
Each DQMi masks 8 DQi's. (1 Byte, 1 Pixel for 8bbp). 2. DQM makes data out Hi-Z after 2 clocks which should masked by CKE "L".
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3. CAS Interrupt (I)
1) Read intreupted by Read (BL=4) Note 1 CKL CMD ADD DQ(CL2) DQ(CL3) tCCD
Note2
RD A
RD B QA0 QB0 QA0 QB1 QB2 QB0 QB1 QB3 QB2 QB3
2) Write interrupted by (Block) Write (BL =2) CKL CMD WR WR
Note2
3) Write interrupted by Read (BL =2)
WR
BW
Note2
WR tCCD A
Note4
RD
Note2
tCCD ADD DQ A DA0 B
tCCD C D
B QB0 Pixel QB0 QB1
DB0
DB1
DC0
Pixel
DQ(CL2) DQ(CL3)
DA0 DA0 tCDL
Note3
tCDL
Note3
tCDL
Note3
2) Block Write to Block Write CKL CMD ADD DQ BW A BW B
Note4
Pixel Pixel tBWC
Note5
Note : 1. By "Interrupt", It is possible to stop burst read/write by external command before the end of burst. By " CAS Interrupt", to stop burst read/write by CAS access; read, write and block write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. ( = 1CLK). 4. Pixel : Pixel mask. 5. tBWC : Block write minimum cycle time.
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4. CAS Interrupt (II) : Read Interrupted Write & DQM
(1) CL=2, BL=4 CLK i) CMD DQM DQ ii) CMD RD D0 D1 WR D2 D3 RD WR
DQM DQ iii) CMD DQM DQ iv) CMD DQM DQ (2) CL=3, BL=4 CLK RD RD
Hi-Z
D0
D1 WR
D2
D3
Hi-Z D0 D1 WR D2 D3
Q0
Hi-Z
Note 1
D0
D1
D2
D3
i) CMD DQM DQ ii) CMD DQM DQ iii) CMD DQM DQ iv) CMD DQM
RD
WR
D0 RD
D1 WR
D2
D3
D0 RD
D1 WR
D2
D3
D0 WR RD
D1 WR
D2
D3
Hi-Z DQ v) CMD DQM DQ Q0 RD
D0
D1 WR
D2
D3
Hi-Z
Note 2
D0
D1
D2
D3
* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out. 2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.
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5. Write Interrupted by Precharge & DQM
CLK
Note 2
CMD DQM DQ
WR
PRE
Note 1
D0
D1
D2
D3
Masked by DQM
Note : 1. To inhibit invalid write, DQM should be issued. 2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual banks operation.
6. Precharge
1) Normal Write (BL=4) CLK CMD DQ WR D0 D1 D2 D3 tRDL
Note 1
2) Block Write CLK PRE CMD DQ BW Pixel tBPL
Note 1
PRE
3) Read (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD Q0 Q1 Q0 PRE Q2 Q1 Q3 Q2
Note 2 1
Q3
2
7. Auto Precharge
1) Normal Write (BL=4) CLK CMD DQ WR D0 D1 D2 D3
Note 3 Auto Precharge Starts
2) Block Write CLK CMD DQ (CL 2,3) BW Pixel tBPL
Note 3
tRP
3) Read (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD Q0 Q1 Q0 Q2 Q1 Q3 Q2
Note 3 Auto Precharge Starts
Auto Precharge Starts
Q3
* Note : 1. tBPL : Block write data-in to PRE command delay. 2. Number of valid output data after Row Precharge : 1,2 for CAS Latency = 2,3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other active bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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8. Burst Stop & Precharge Interrupt
1) Write Interrupted by Precharge (BL=4) CLK CMD DQM DQ D0 D1 D2 D3 tRDL
Note 1
2) Write Burst Stop (Full Page Only) CLK
WR
PRE
CMD
WR
STOP
DQ
D0
D1
D2 tBDL
3) Read Interrupted by Precharge (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD PRE Q0 Q1 Q0
Note 3 1
4) Read Burst Stop (Full Page Only) CLK CMD DQ(CL2) Q1
2
RD
STOP Q0 Q1 Q0
Note 3 1
DQ(CL3)
Q1
2
9. MRS & SMRS
2) Mode Register Set CLK
Note 4
2) Special Mode Register Set CLK
CMD
PRE tRP
MRS
ACT
CMD
SMRS ACT SMRS SMRS
BW
1CLK
1CLK 1CLK 1CLK 1CLK
Note : 1.tRDL : 2CLK, Last Data in to Row Precharge. 2. tBDL : 1CLK, Last Data in to Burst Stop Delay. 3. Number of valid output data after Row precharge or burst stop : 1,2 for CAS latency=2,3 respectively. 4. PRE : Both banks precharge if necessary. MRS can be issued only at all bank precharge state.
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10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal CLK CMD
Note 1
2) Power Down (=Precharge Power Down) Exit CLK
tSS
CKE Internal CLK RD CMD
Note 2
tSS
NOP
ACT
11. Auto Refresh & Self Refresh
Note 3
1) Auto Refresh
CKE Internal CLK CMD
Note 4
~ ~
CLK PRE AR
Note 5
CMD
tRP
tRC
Note 6
2) Self Refresh
Note 4
CMD CKE
PRE
SR
~ ~
CLK
~ ~
~~ ~~
~ ~
tRP
tRC
* Note : 1. Active power down : one or more bank active state. 2. Precharge power down : both bank precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after Auto Refresh command. During tRC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, both banks must be idle state. 5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh mode, refresh interval and refresh operation are performed internally. After self refresh entry, self refresh mode is kept while CKE is LOW. During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state. During tRC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst auto refresh cycle (2K cycles ) is recommended.
~ ~
~ ~
~ ~
CMD
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12. About Burst Type Control
Basic MODE Sequential counting Interleave counting At MRS A3="0". See the BURST SEQUENCE TABE.(BL=4,8) BL=1,2,4,8 and full page wrap around. At MRS A3=" 1". See the BURST SEQUENCE TABE.(BL=4,8) BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting At MRS A3 = "1". (See to Interleave Counting Mode) Starting Address LSB 3 bits A0-2 should be "000" or "111".@BL=8. --if LSB = "000" : Increment Counting. --if LSB= "111" : Decrement Counting. For Example, (Assume Addresses except LSB 3 bits are all 0, BL=8) --@ write, LSB="000", Accessed Column in order 0-1-2-3-4-5-6-7 --@ read, LSB="111", Accessed Column in order 7-6-5-4-3-2-1-0 At BL=4, same applications are possible. As above example, at Interleave Counting mode, by confining starting address to some values, PseudoDecrement Counting Mode can be realized. See the BURST SEQUENCE TABLE carefully. At MRS A3 = "0". (See to Sequential Counting Mode) A0-2 = "111". (See to Full Page Mode) Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be realized. --@ Sequential Counting Accessed Column in order 3-4-5-6-7-1-2-3 (BL=8) --@ Pseudo-Binary Counting, Accessed Column in order 3-4-5-6-7-8-9-10 (Burst Stop command) Note. The next column address of 256 is 0 Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of convention DRAM.
PseudoDecrement Sequential Counting
PseudoMODE
Pseudo-Binary Counting
Random MODE
Random column Access tCCD = 1 CLK
13. About Burst Length Control
At MRS A2,1,0 = "000". At auto precharge, tRAS should not be violated. At MRS A2,1,0 = "001". 2 At auto precharge, tRAS should not be violated. 4 At MRS A2,1,0 = "010" 8 At MRS A2,1,0 = "011". At MRS A2,1,0 = "111". Full Page Wrap around mode (Infinite burst length) should be stopped by burst stop, RAS interrupt or CAS interrupt. At MRS A9="1". BRSW Read burst = 1,2,4,8, full page/write Burst =1 At auto precharge of write, tRAS should not be violated. 8 Column Block Write. LSB A0-2 are ignored. Burst length=1. Block Write tBWC should not be violated. At auto precharge, tRAS should not be violated. tBDL=1, Valid DQ after burst stop is 1,2 for CL=2,3 respectively Burst Stop Using burst stop command, it is possible only at full page burst length. Before the end of burst, Row precharge command of the same bank RAS Interrupt Stops read/write burst with Row precharge. (Interrupted by Precharge) tRDL=2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively During read/write burst with auto precharge, RAS interrupt cannot be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. CAS Interrupt During read/write burst with auto precharge, CAS interrupt can not be issued. 1
Basic MODE
Special MODE
Random MODE
Interrupt MODE
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14. Mask Functions
1) Normal Write I/O masking : By Mask at Write per Bit Mode, the selected bit planes keep the original data. If bit plane 0,3,7,9,15,22,24, and 31 keep the original value. i) STEP ** SMRS (LMR) : Load mask [31-0]="0111,1110,1011,1111,0111,1101,0111,0110" ** Row Active with DSF "H" : Writ Per Bit Mode Enable ** Perform Normal Write ii) ILLUSTRATION I/O(=DQ) External Data-in DQMi Mask Register Before Write After Write 31 24 11111111 DQM3=0 01111110 00000000 01111110 23 16 11111111 DQM2=0 10111111 00000000 10111111 15 8 0000000 DQM1=0 0111101 1111111 1000010 7 0 00000000 DQM0=1 01110110 11111111 11111111 Note 1
2) Block Write Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data. See PIXEL TO DQ MAPPING TABLE. If Pixel 0,4,9,13,18, 22, 27 and 31 keep the original white color. Assume 8bpp, White = "0000,0000", Red = "1010,0011", Green = "1110,0001", Yellow = "0000,1111", Blue = "1100,0011" i) STEP ** SMRS(LCR) : Load color (for 8bbp, through X32 DQ color 0-3 are loaded into color registers) Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red) = "1100,0011,1110,0001,0000,1111,1010,0011" ** Row Active with DSF "L" : I/O Mask by Write Per Bit Mode Disable ** Block write with DQ[31-0] = "0111,0111,1011,1011,1101,1101,1110,1110" ii) ILLUSTRATION I/O(=DQ) 31 24 23 16 15 8 7 0 DQMi DQM3=0 DQM2=0 DQM1=0 DQM0=1 Color Register Color3=Blue Color2=Green Color1=Yellow Color0=Red 000 White DQ24=H White DQ16=H White DQ8=H White DQ0=L Before 001 White DQ25=H White DQ17=H White DQ9=L White DQ1=H Block 010 White DQ26=H White DQ18=L White DQ10=H White DQ2=H Write 011 White DQ27=L White DQ19=H White DQ11=H White DQ3=H & 100 White DQ28=H White DQ20=H White DQ12=H White DQ4=L DQ 101 White DQ29=H White DQ21=H White DQ13=L White DQ5=H (Pixel 110 White DQ30=H White DQ22=L White DQ14=H White DQ6=H data) 111 White DQ31=L White DQ23=H White DQ15=H White DQ7=H 000 Blue Green Yellow White 001 Blue Green White White 010 Blue White Yellow White After 011 White Green Yellow White Block 100 Blue Green Yellow White Write 101 Blue Green White White 110 Blue White Yellow White 111 White Green Yellow White Note 2 * Note : 1. DQM byte masking. 2. At normal write, One column is selected among columns decoded by A2-0 (000-111) At block write, instead of ignored address A2-0, DQ0-31 control each pixel.
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A45L9332A Series
(Continued)
Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data. By Pixel Data issued through DQ pin, the selected pixels keep the original data. See PIXEL TO DQ MAPPING TANLE. Assume 8bpp, White = "0000,0000", Red = "1010,0011", Green = "1110,0001", Yellow = "0000,1111", Blue = "1100,0011" i) STEP ** SMRS (LCR) : Load color (for 8bpp, through X 32 DQ color0-3 are loaded into color registers) Load (color3, color2, color1, color0) = (Blue, Green, Yellow, Red) = "1100,0011,1110,0001,0000,1111,1010,0011" **SMRS (LMR) : Load mask, Mask[31-0] = "1111,1111,1101,1101,0100,0010,0111,0110" Byte 3:No I/O Masking; Byte 2:I/O Masking; Byte 1:I/O and Pixel Masking; Byte 0:DQM Byte Masking ** Row Active with DSF "H" : I/O Mask by Write Per Bit Mode Enable ** Block Write with DQ[31-0] = "0111,0111,1111,1111,0101,0101,1110,1110" (Pixel Mask) ii) ILLUSTRATUON I/O(=DQ) Color Register DQMi Mask Register Before Write After Write 31 24 Blue 11000011 DQM3=0 11111111 Yellow 00001111 Blue 11000011 16 Green 11100001 DQM2=0 11011101 Yellow 00001111 Blue 11000011 23 8 Yellow 00001111 DQM1=0 01000010 Green 11100001 Red 10100011 15 0 Red 10100011 DQM0=1 01110110 White 00000000 White 00000000 Note 1 I/O(=DQ) 31 24 DQMi DQM3=0 Color Register Color3=Blue 000 Yellow DQ24=H Before 001 Yellow DQ25=H Block 010 Yellow DQ26=H Write 011 Yellow DQ27=L & 100 Yellow DQ28=H DQ 101 Yellow DQ29=H (Pixel 110 Yellow DQ30=H data) 111 Yellow DQ31=L 000 Blue 001 Blue 010 Blue After 011 Yellow Block 100 Blue Write 101 Blue 110 Blue 111 Yellow Note 2 PIXEL MASK 16 DQM2=0 Color2=Green Yellow DQ16=H Yellow DQ17=H Yellow DQ18=H Yellow DQ19=H Yellow DQ20=H Yellow DQ21=H Yellow DQ22=H Yellow DQ23=H Blue Blue Blue Blue Blue Blue Blue Blue 23 8 DQM1=0 Color1=Yellow Green DQ8=H Green DQ9=L Green DQ10=H Green DQ11=H Green DQ12=H Green DQ13=L Green DQ14=H Green DQ15=L Red Green Red Green Red Green Red Green 15 0 DQM0=1 Color0=Red White DQ0=L White DQ1=H White DQ2=H White DQ3=H White DQ4=L White DQ5=H White DQ6=H White DQ7=H White White White White White White White White Note 1 BYTE MASK 7 7
I/O MASK
PIXEL & I/O MASK
* Note : 1. DQM byte masking. 2. At normal write, One column is selected among columns decoded by A2-0 (000-111) At block write, instead of ignored address A2-0, DQ0-31 control each pixel.
PRELIMINARY
(October, 2001, Version 0.1)
27
AMIC Technology, Inc.
A45L9332A Series
Power On Sequence & Auto Refresh
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
High level is necessary
~
CS tRP RAS
tRC
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
~ ~
DQM
High level is necessary
~ ~
DQ
Precharge (All Banks)
Auto Refresh
Auto Refresh
~ ~
High-Z
~ ~
~ ~
DSF
~ ~
WE
~ ~
A9/AP
~ ~
A10/BA
~ ~
ADDR
~ ~ ~ ~
CAS
~ ~ ~ ~
~ ~ ~
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
KEY
Ra
~ ~ ~ ~ ~ ~ ~ ~
KEY
BS
KEY
Ra
Mode Regiser Set Row Active (Write per Bit Enable or Disable)
: Don't care
PRELIMINARY
(October, 2001, Version 0.1)
28
AMIC Technology, Inc.
A45L9332A Series
Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1
tCH 0 CLOCK tCC CKE tRAS tRC
*Note 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tCL High
tSH tSS
CS tRCD tSH RAS tSS tSH CAS tSS tSH ADDR tSS
*Note 2 *Note 2,3
tRP
tCCD
tSS Ca Cb tSH
*Note 2,3 *Note 2,3 *Note 4 *Note 2
Ra
Cc
Rb
A10
BS
BS
BS
BS
BS
BS
*Note 3
*Note 3
*Note 3
*Note 4
A9
Ra
Rb
tSH WE tSS
*Note 5 *Note 6 *Note 3 *Note 5
DSF tSS tSH tSS DQM tRAC tSAC DQ tSLZ tOH Qa tSS tSHZ
tSH
tSH Db Qc
Row Active (Write per Bit Enable or Disable)
Read
Write or Block Write
Read Precharge
Row Active (Write per Bit Enable or Disable : Don't care
PRELIMINARY
(October, 2001, Version 0.1)
29
AMIC Technology, Inc.
A45L9332A Series
* Note : 1. All inputs can be don't care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by A10.
A10 0 1
Active & Read/Write Bank A Bank B
3. Enable and disable auto precharge function are controlled by A9 in read/write command. A9 0 A10 0 1 0 1 1 Operation Disable auto precharge, leave bank A active at end of burst. Disable auto precharge, leave bank B active at end of burst. Enable auto precharge, precharge bank A at end of burst. Enable auto precharge, precharge bank B at end of burst.
4. A9 and A10 control bank precharge when precharge command is asserted. A9 0 0 1 A10 0 1 X Precharge Bank A Bank B Both Bank
5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command. A10 0 DSF L H L 1 H Operation Bank A row active, disable write per bit function for bank A Bank A row active, enable write per bit function for bank A Bank B row active, disable write per bit function for bank B Bank B row active, enable write per bit function for bank B
6. Block write/normal write is controlled by DSF DSF L H Operation Normal write Block write Minimum cycle time tCCD tBWC
PRELIMINARY
(October, 2001, Version 0.1)
30
AMIC Technology, Inc.
A45L9332A Series
Read & Write Cycle at Same Bank @Burst Length=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE tRC CS tRCD *Note 1
High
RAS *Note 2 CAS
ADDR
Ra
Ca0
Rb
Cb0
A10
A9
Ra
Rb
WE
DSF
DQM tOH DQ (CL = 2) Qa0 tRAC *Note 3 tSAC tOH DQ (CL = 3) Qa0 tRAC *Note 3 tSAC Qa1 Qa2 Qa3 tSHZ *Note 4 Db0 Db1 Db2 tRDL Db3 Qa1 Qa2 Qa3 *Note 4 Db0 Db1 Db2 tRDL Db3
tSHZ
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Row Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank) : Don't care
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row enters precharge. Last valid output will be Hi-Z after tSHZ from the clock. 3. Access time from Row address. tCC*(tRCD + CAS latency-1) + tSAC 4. Output will be Hi-Z after the end of burst. (1,2,4 & 8) At Full page bit burst, burst is wrap-around.
PRELIMINARY
(October, 2001, Version 0.1)
31
AMIC Technology, Inc.
A45L9332A Series
Page Read & Write Cycle at Same Bank @Burst Length=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
High
CS tRCD
RAS *Note 2 CAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
A10
A9
Ra tCDL tRDL
WE *Note 2
DSF *Note1 DQM *Note3
DQ (CL=2)
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
DQ (CL=3)
Qa0
Qa1
Qb0
Dc0
Dc1
Dd0
Dd1
Row Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
: Don't care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.
PRELIMINARY
(October, 2001, Version 0.1)
32
AMIC Technology, Inc.
A45L9332A Series
Block Write Cycle (with Auto Precharge)
0 CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
High
CS
RAS
CAS *Note 2 ADDR RAa CAa CAb RBa CBa CBb
A10
A9
RAa
RBa
WE
DSF tBWC
DQM *Note 1 DQ
Pixel Mask Pixel Mask Pixel Mask Pixel Mask
Row Active with Write-per-Bit Enable (A-Bank)
Masked Block Write (A-Bank) Masked Block Write with Auto Precharge (A-Bank)
Row Active (B-Bank)
Block Write with Auto Precharge (B-Bank) Block Write (B-Bank) : Don't care
*Note : 1. Column Mask (DQi=L : Mask, DQi=H : Non Mask) 2. At Block Write, CA0-2 are ignored.
PRELIMINARY
(October, 2001, Version 0.1)
33
AMIC Technology, Inc.
A45L9332A Series
SMRS and Block/Normal Write @ Burst Length=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
High
CS
RAS
CAS *Note1 A0-2 RAa RBa CBa
A3,4,7,8
RAa
CAa
RBa
CBa
A5
RAa
CAa
RBa
CBa
A6
RAa
CAa
RBa
CBa
A9
RAa
CAa
A10
WE
DSF
DQM
DQ
Color
I/O Mask
Pixel Mask
I/O Mask
Color
DBa0
DBa1
DBa2
DBa3
Load Color Register
Load Color Register Masked Bolck Write (A-Bank)
Row Active with WPB* Enable (A-Bank)
Row Active with WPB* Enable (B-Bank)
Load Color Register Masked Write with Auto Precharge (B-Bank)
WPB* : Write-Per-Bit
Load Mask Register
: Don't care
* Note : 1. At the next clock of special mode set command, new command is possible.
PRELIMINARY
(October, 2001, Version 0.1)
34
AMIC Technology, Inc.
A45L9332A Series
Page Read Cycle at Different Bank @Burst Length = 4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
*Note 1
High
CS
RAS
*Note 2
CAS
ADDR
RAa
CAa
RBb
CBb
CAc
CBd
CAe
A10
A9 WE
RAa
RBb
DSF
Low
DQM
DQ (CL=2)
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
DQ (CL=3)
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
Row Active (A-Bank)
Row Active (B-Bank) Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Read (B-Bank)
Read (A-Bank)
Precharge (A-Bank)
: Don't care
* Note : 1. CS can be don't care when RAS, CAS and
WE
are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.
PRELIMINARY
(October, 2001, Version 0.1)
35
AMIC Technology, Inc.
A45L9332A Series
Page Write Cycle at Different Bank @Burst Length=4
0 CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
High
CS
RAS
CAS
ADDR
RAa
Key
CAa
RBb
CBb
CAc
CBd
A10
A9
RAa
RBb tCDL
WE
DSF
DQM
DQ
Mask
DAa0 DAa1 DAa2
DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DAc2 DAc3 DBd0 DBd1 DBd2 DBd3
Load Mask Register Row Active with Write-Per-Bit enable (A-Bank)
Row Active (B-Bank) Masked Write (A-Bank)
Write (B-Bank)
Masked Write with auto precharge (A-Bank)
Write with auto Precharge (B-Bank)
: Don't care
PRELIMINARY
(October, 2001, Version 0.1)
36
AMIC Technology, Inc.
A45L9332A Series
Read & Write Cycle at Different Bank @Burst Length=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
High
CS
RAS
CAS
ADDR
RAa
CAa
RBb
CBb
RAc
CAc
A10
A9
RAa
RBb
RAc tCDL *Note 1
WE
DSF
DQM
DQ (CL=2)
QAa0
QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
DQ (CL=3)
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Write (B-Bank)
Read (A-Bank)
Row Active (B-Bank)
Row Active (A-Bank) : Don't care
* Note : 1. tCDL should be met to complete write.
PRELIMINARY
(October, 2001, Version 0.1)
37
AMIC Technology, Inc.
A45L9332A Series
Read & Write Cycle with Auto Precharge I @Burst Length=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
High
CS
RAS
CAS
ADDR
RAa
RBb
CAa
CBb
A10
A9
RAa
RBb
WE
DSF
DQMi
DQ (CL=2)
QAa0
QAa1
QAa2 QAa3
DBb0
DBb1
DBb2
DBb3
DQ (CL=3)
QAa0
QAa1 QAa2
QAa3
DBb0
DBb1
DBb2
DBb3
Row Active (A-Bank)
Read with Auto Precharge (A-Bank) Row Active (B-Bank)
Auto Precharge Start Point (A-Bank)
Write with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
: Don't care
*Note : 1. tRCD should be controlled to meet minimum tRAS before internal precharge start. (In the case of Burst Length=1 & 2, BRSW mode and Block write)
PRELIMINARY
(October, 2001, Version 0.1)
38
AMIC Technology, Inc.
A45L9332A Series
Read & Write Cycle with Auto Precharge II @Burst Length=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
High
CS
RAS
CAS
ADDR
Ra
Rb
Ca
Cb
Ra
Ca
A10
A9
Ra
Rb
Ra
WE
DSF
DQM
DQ (CL=2)
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
Da0
Da1
DQ (CL=3)
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
Da0
Da1
Row Active (A-Bank)
Read with Auto Pre Charge (A-Bank)
Read without Auto Precharge (B-Bank) Auto Precharge Strart Point (A-Bank) *Note 1
Precharge (B-Bank)
Row Active (A-Bank)
Write with Auto Precharge (A-Bank)
Row Active (B-Bank) : Don't care
* Note : 1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. - if read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank auto precharge will start at B Bank read command input point. - Any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
PRELIMINARY
(October, 2001, Version 0.1)
39
AMIC Technology, Inc.
A45L9332A Series
Read & Write Cycle with Auto Precharge III @Burst Length=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
High
CS
RAS
CAS
ADDR
Ra
Ca
Rb
Cb
A10
A9
Ra
Rb
WE
DSF
DQM
DQ (CL=2)
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
DQ (CL=3)
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Db2
Db3
* Note 1
Row Active (A-Bank)
Read with Auto Preharge (A-Bank)
Auto Precharge Read with Start Point Auto Precharge (B-Bank) (A-Bank) Row Active (B-Bank)
Auto Precharge Start Point (B-Bank)
: Don't care
* Note : 1. Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point
PRELIMINARY
(October, 2001, Version 0.1)
40
AMIC Technology, Inc.
A45L9332A Series
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full Page Only)
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
High
CS
RAS
CAS
ADDR
RAa
CAa
CAb
A10
* Note 1 * Note 1
A9
RAa
WE
DSF
DQM
* Note 2
1
1
DQ (CL=2)
QAa0
QAa1
QAa2
QAa3 QAa4
QAb0 QAb1 QAb2 QAb3
QAb4 QAb5
2
2
DQ (CL=3)
QAa0
QAa1
QAa2 QAa3 QAa4
QAb0 QAb1
QAb2 QAb3
QAb4
QAb5
Row Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
: Don't care
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. About the valid DQ's after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycle".
PRELIMINARY
(October, 2001, Version 0.1)
41
AMIC Technology, Inc.
A45L9332A Series
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full Page Only)
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
High
CS
RAS
CAS
ADDR
RAa
CAa
CAb
A10
* Note 1 * Note 1
A9
RAa tBDL tRDL
WE
DSF
* Note 3
DQM
* Note 2
DQ
DAa0 DAa1
DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
Row Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
: Don't care
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. Data-in at the cycle of burst stop command cannot be written into corresponding memory cell. It is defined by AC parameter of tBDL(=1CLK). 3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell. It is defined by AC parameter of tRDL(2=CLK). DQM at write interrupted by precharge command is needed to ensure tRDL of 2CLK. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 4. Burst stop is valid only at full page burst length.
PRELIMINARY
(October, 2001, Version 0.1)
42
AMIC Technology, Inc.
A45L9332A Series
Burst Read Single Bit Write Cycle @Burst Length=2, BRSW
0 CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
High
CS
RAS
* Note 2
CAS
ADDR
RAa
CAa
RBb
CAb
RAc
CBc
CAd
A10
A9
RAa
RBb
RAc
WE
DSF
DQM
DQ (CL=2)
DAa0
QAb0
QAb1
DBc0
QAd0
QAd1
DQ (CL=3)
DAa0
QAb0 QAb1
DBc0
QAd0
QAd1
Row Active (A-Bank)
Row Active (B-Bank)
Row Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Write (A-Bank)
Read with Auto Precharge (A-Bank)
Write with Auto Precharge (B-Bank) : Don't care
* Note : 1. BRSW mode is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regardless of programed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, The next cycle starts the precharge. 3. WPB function is also possible at BRSW mode.
PRELIMINARY
(October, 2001, Version 0.1)
43
AMIC Technology, Inc.
A45L9332A Series
Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4
0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
A10
A9
Ra
WE
DSF
* Note 1
DQM
DQ
Qa0
Qa1
Qa2
Qa3 tSHZ
Qb0
Qb1 tSHZ
Dc0
Dc2
Row Active
Read
Clock Suspension
Read
Read DQM Write
Write DQM Clock Suspension
: Don't care * Note : 1. DQM needed to prevent bus contention.
PRELIMINARY
(October, 2001, Version 0.1)
44
AMIC Technology, Inc.
A45L9332A Series
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
0 CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
~ ~
* Note 2
tSS CKE
* Note 1
tSS
tSS
~ ~
tSS Ra
*Note 3
~ ~
CS
~ ~
CAS
~ ~
~ ~ ~ ~
~ ~ ~ ~
RAS
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
~ ~
Ca
~ ~
~ ~
~ ~
~ ~
~ ~
DSF
~ ~
~ ~
DQ
~ ~
~ ~
DQM
~ ~ ~ ~
~ ~ ~ ~
WE
~ ~ ~ ~
A9
Ra
~ ~ ~ ~
A10
~ ~ ~ ~
ADDR
~ ~ ~ ~ ~ ~ ~ ~ ~ ~
Precharge Power-down Entry Precharge Power-down Exit Row Active Active Power-down Entry
Qa0
Qa1
Qa2
Read
Precharge
Active Power-down Exit : Don't care
* Note : 1. All banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least "1CLK + tSS" prior to Row active command. 3. Cannot violate minimum refresh specification. (32ms)
PRELIMINARY
(October, 2001, Version 0.1)
45
AMIC Technology, Inc.
A45L9332A Series
Self Refresh Entry & Exit Cycle
0 CLOCK
* Note 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
~ ~
* Note 4
* Note 1
* Note 3
tSS CS
* Note 5
~ ~
~ ~
~ ~
* Note 7
~ ~
RAS
~ ~ ~ ~
~ ~
CKE
tSS
tRC min.
* Note 6
~ ~
~ ~ ~ ~ ~ ~ ~ ~
* Note 7
~ ~
CAS
~ ~
~ ~
~ ~
~ ~
~ ~
DSF
~ ~
~ ~
DQ
Hi-Z
Hi-Z
Self Refresh Entry
Self Refresh Exit
~ ~
~ ~
DQM
~ ~ ~ ~
WE
~ ~ ~ ~
A9
~ ~ ~ ~
A10
~ ~ ~ ~
ADDR
~ ~ ~ ~
* Note : TO ENTER SELF REFRESH MODE 1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". (cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System clock restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit. If the system uses burst refresh.
~ ~ ~ ~ ~ ~ ~ ~ ~ ~
Auto Refresh : Don't care
PRELIMINARY
(October, 2001, Version 0.1)
46
AMIC Technology, Inc.
A45L9332A Series
Mode Register Set Cycle
0 CLOCK 1 2 3 4 5 6
Auto Refresh Cycle
0 1 2 3 4 5 6 7 8 9 10
CKE *Note 2 CS
High
High
tRC RAS
* Note 1
CAS
* Note 3
MRS New Command
Auto Refresh
~ ~
DQ
Hi-Z
Hi-Z
~ ~
DQM
~ ~ ~ ~
DSF
~ ~ ~ ~
WE
~ ~ ~ ~
ADDR
Key
Ra
~ ~ ~ ~
New Command : Don't care
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE * Note : 1. CS , RAS , CAS & mode register.
WE
activation and DSF of low at the same clock cycle with address key will set internal
2. Minimum 1 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
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AMIC Technology, Inc.
~ ~ ~ ~
~ ~ ~ ~
~ ~
~ ~
~ ~
A45L9332A Series
Function Truth Table (Table 1)
Current State
CS
H L L L L L L L L L L L H L L L L L L L L L L L L H L L L L L L L L L L L
RAS CAS
X H H H L L L L L L L L X H H H H H H L L L L L L X H H H H H H H L L L L X H H L H H H H L L L L X H H L L L L H H H L L L X H H H L L L L H H H L
WE
X H L X H H L L H H L L X H L H H L L H L L H L L X H L L H H L L H L L X
DSF X X X X L H L H L H L H X X X L H L H X L H X L H X X L H L H L H X L H X
BA Address (A10) X X X BA BA BA BA X X X X X X CA RA RA PA X X X OP Code OP Code X X X BA X BA BA BA BA X X X X X X X BA X BA BA BA BA X X X X X CA,AP X CA,AP CA,AP RA PA X X X OP Code X X X X CA,AP X CA,AP CA,AP RA PA X X NOP NOP ILLEGAL ILLEGAL
Action
Note
2 2
Row Active; Latch Row Address; Non-IO Mask Row Active; latch Row Address; IO Mask NOP ILLEGAL Auto Refresh or Self Refresh ILLEGAL Mode Register Access Special Mode Register Access NOP NOP ILLEGAL Begin Read; Latch CA; Determine AP ILLEGAL Begin Write; Latch CA; Determine AP Block Write; Latch CA; Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL ILLEGAL Special Mode Register Access NOP(Continue Burst to End Row Active) NOP(Continue Burst to End Row Active) Term burst Row Active ILLEGAL Term burst; Begin Read; Latch CA; Determine AP ILLEGAL Term burst; Begin Write; Latch CA; Determine AP Term burst; Block Write; Latch CA; Determine AP ILLEGAL Term Burst; Precharge timing for Reads ILLEGAL ILLEGAL 3 3 2 3 3 6 2 2 5 6 5 4
IDLE
Row Active
Read
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AMIC Technology, Inc.
A45L9332A Series
Function Truth Table (Table 1, Continued)
Current State
CS
H L L L L
RAS CAS
X H H H H H H H L L L L X H H H H L L X H H H H L L X H H H L L L X H H H L L L L H H H L X H H L L H L X H H L L H L X H H L H H L
WE
X H L L H H L L H L L X X H L H L X X X H L H L X X X H L X H L X
DSF X X L H L H L H X L H X X X X X X X X X X X X X X X X X X X X X X
BA Address (A10) X X X X BA X BA BA BA BA X X X X X BA BA BA X X X X BA BA BA X X X X BA BA BA X X X X X CA,AP X CA,AP CA,AP RA PA X X X X X CA,AP CA,AP RA,PA X X X X CA,AP CA,AP RA,PA X X X X CA,AP RA PA X
Action NOP(Continue Burst to EndRow Active) NOP(Continue Burst to EndRow Active) Term burst Row Active) ILLEGAL Term burst; Begin Read; Latch CA; Determine AP ILLEGAL Term burst; Begin Write; Latch CA; Determine AP Term burst; Block Write; Latch CA; Determine AP ILLEGAL Term Burst; Precharge timing for Writes ILLEGAL ILLEGAL NOP(Continue Burst to EndPrecharge) NOP(Continue Burst to EndPrecharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP(Continue Burst to EndPrecharge) NOP(Continue Burst to EndPrecharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOPIdle after tRP NOPIdle after tRP ILLEGAL ILLEGAL ILLEGAL NOPIdle after tRP ILLEGAL
Note
3 3 3 2 3
Write
L L L L L L L H L
Read with Auto Precharge
L L L L L H L
2 2 2
Write with Auto Precharge
L L L L L H L
2 2 2
Precharge
L L L L L
2 2 2 4
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AMIC Technology, Inc.
A45L9332A Series
Function Truth Table (Table 1, Continued)
Current State
CS
H L
RAS CAS
X H H H L L L X H H H L L L X H H L L X H H L H H L X H H L H H L X H L H L
WE
X H L X H L X X H L X H L X X X X X X
DSF X X X X X X X X X X X X X X X X X X X
BA Address (A10) X X X BA BA BA X X X X BA BA BA X X X X X X X X X RA PA X X X X RA PA X X X X X X
Action NOPRow Active after tBWC NOPRow Active after tBWC ILLEGAL
Note
Block Write Recovering
L L L L L H L
CA,AP ILLEGAL ILLEGAL Term Block Write: Precharge timing for Block Write ILLEGAL NOPRow Active after tRCD NOPRow Active after tRCD ILLEGAL
2 2 2 2
Row Activating
L L L L L H L
CA,AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOPIdle after tRC NOPIdle after tRC ILLEGAL ILLEGAL ILLEGAL
2 2 2 2
Refreshing
L L L
Abbreviations RA = Row Address (A0~A9) NOP = No Operation Command
BA = Bank Address (A10) CA = Column Address (A0~A7)
PA = Precharge All (A9) AP = Auto Precharge (A9)
Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle. 2. Illegal to bank in specified state : Function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA). 5. Illegal if any banks is not idle. 6. Legal only if all banks are in idle or row active state.
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AMIC Technology, Inc.
A45L9332A Series
Function Truth Table for CKE (Table 2)
Current State CKE n-1 H L L Self Refresh L L L L H Both Bank Precharge Power Down L L L L L L H H H All Banks Idle H H H H H L Any State Other than Listed Above H H L L CKE n X H H H H H L X H H H H H L H L L L L L L L L H L H L
CS
X H L L L L X X H L L L L X X H L L L L L L X X X X X
RAS CAS
X X H H H L X X X H H H L X X X H H H L L L X X X X X X X H H L X X X X H H L X X X X H H L H L L X X X X X
WE
X X H L X X X X X H L X X X X X H L X X H L X X X X X
DSF X X X X X X X X X X X X X X X X X X X X L X X X X X X
Address X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID
Action
Note
Exit Self RefreshABI after tRC Exit Self RefreshABI after tRC ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Self Refresh) INVALID Exit Power DownABI Exit Power DownABI ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power Down Mode) Refer to Table 1 Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table 1 Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain clock Suspend
7 7
8 8
9 9
9
10 10
Abbreviations : ABI = All Banks Idle Note: 7. After CKE's low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE's low to high transition to issue a new command. 8. CKE low to high transition is asynchronous as if restarts internal clock. A minimum setup time "tSS + one clock" must be satisfied before any command other than exit. 9. Power-down and self refresh can be entered only from the all banks idle state. 10. Must be a legal command.
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A45L9332A Series
Ordering Information
Part No. A45L9332AF-6 A45L9332AE-6 A45L9332AF-7 A45L9332AE-7 A45L9332AF-8 A45L9332AE-8 * QFP (Height = 3.0mm Max) LQFP (Height = 1.4mm Max) Cycle Time (ns) 6 6 7 7 8 8 Clock Frequency (MHz) 166 166 143 143 125 125 Access Time 5.5 ns @ CL = 3 5.5 ns @ CL = 3 6.0 ns @ CL = 3 6.0 ns @ CL = 3 6.5 ns @ CL = 3 6.5 ns @ CL = 3 Package 100 QFP 100 LQFP 100 QFP 100 LQFP 100 QFP 100 LQFP
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A45L9332A Series
Package Information QFP 100L Outline Dimensions
unit: inches/mm
HE E
80 51
A2
A1 y D
81
50
HD D
100
31
1
30
e
b
c
Symbol A1 A2 b c HE E HD D e L L1 y
Dimensions in inches Min. 0.004 0.107 0.010 0.0057 0.905 0.783 0.669 0.547 0.020 0.025 0.057 0 Nom. 0.112 0.006 0.913 0.787 0.677 0.551 0.026 0.031 0.063 Max. 0.117 0.014 0.0063 0.921 0.791 0.685 0.555 0.032 0.037 0.069 0.004 8
Dimensions in mm Min. 0.100 2.723 0.26 0.142 22.950 19.900 16.950 13.900 0.500 0.650 1.450 0 Nom. 2.85 0.150 23.200 20.000 17.200 14.000 0.650 0.800 1.600 Max. 2.977 0.36 0.158 23.450 20.100 17.450 14.100 0.800 0.950 1.750 0.100 8
Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
L
L1
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.
A45L9332A Series
Package Information LQFP 100L Outline Dimensions
unit: inches/mm
HE E
80 51
A2
A1 y D
81
50
HD D
100
31
1
30
e
b
c
Symbol A1 A2 b c HE E HD D e L L1 y
Dimensions in inches Min. 0.002 0.053 0.011 0.005 0.860 0.783 0.624 0.547 Nom. 0.055 0.013 0.866 0.787 0.630 0.551 0.026 BSC 0.018 0.024 0.039 REF 0 3.5 0.004 7 0.030 Max. 0.057 0.015 0.008 0.872 0.791 0.636 0.555
Dimensions in mm Min. 0.05 1.35 0.27 0.12 21.85 19.90 15.85 13.90 Nom. 1.40 0.32 22.00 20.00 16.00 14.00 0.65 BSC 0.45 0.60 1.00 REF 0 3.5 0.1 7 0.75 Max. 1.45 0.37 0.20 22.15 20.10 16.15 14.10
Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
L
L1
PRELIMINARY
(October, 2001, Version 0.1)
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AMIC Technology, Inc.

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